LCPC'04 will include a Mini Workshop on Compiler infrastructures. A number of compiler infrastructures that are available for download and use by the research community will be presented. The intended audience is students who plan to implement their compilation techniques in a real compiler testbed. The format will be tutorials of 1.5 hrs for four infrastructures, in which students can learn how to use these environments and ask questions to the developers. Attendance of the Mini Workshop is included in the LCPC'04 registration fee.
The goals of the mini workshop are to
| 11:30am-12:00pm | Registration |
| 12:00-1:30pm | From Polaris for Fortran to Cetus for C, C++ and Java |
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Presenters: Rudolf Eigenmann < eigenman@purdue.edu > Troy Johnson < troyj@ecn.purdue.edu > Download site: http://www.ece.purdue.edu/ParaMount/Polaris/download.html http://www.ece.purdue.edu/ParaMount/Cetus/download.html Abstract: Polaris is an established infrastructure for source-to-source translation of Fortran programs. It has been developed at the University of Illinois and Purdue University and is being used by many research groups worldwide. Polaris is written in C++. It is being used for a large number of compiler projects, many of which focus on advanced program analysis, parallelism detection and program restructuring for high-performance shared-memory as well as distributed-memory platforms. The first third of the tutorial will give an overview of Polaris. The remainder of the tutorial will introduce a new infrastructure, Cetus, developed at Purdue University. Cetus aims at restructuring programs in C, C++, and Java. Cetus/C is available for download and will be described in this tutorial. Cetus is implemented in Java. Many Cetus features are modeled after Polaris, the main difference being the representation of an advanced type system, as needed in C and in object-oriented programs. So far, Cetus has been used for projects such as building OpenMP translators, developing pointer analysis techniques, and program instrumentation. | |
| 1:45-3:15pm | The LLVM Compiler Framework and Infrastructure |
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Presenters: Chris Lattner < sabre@nondot.org > Vikram Adve < vadve@cs.uiuc.edu > Download site: http://llvm.cs.uiuc.edu/releases/ Abstract: The Low-Level Virtual Machine (LLVM) is a collection of libraries and tools that make it easy to build compilers, optimizers, Just-In-Time code generators, and many other compiler-related programs. LLVM uses a single, language-independent virtual instruction set both as an offline code representation (to communicate code between compiler phases and to run-time systems) and as the compiler internal representation (to analyze and transform programs). This persistent code representation allows a common set of sophisticated compiler techniques to be applied at compile-time, link-time, install-time, run-time, or "idle-time" (between program runs). The strengths of the LLVM infrastructure are its extremely simple design (which makes it easy to understand and use), source-language independence, powerful mid-level optimizer, automated compiler debugging support, extensibility, and its stability and reliability. LLVM is currently being used to host a wide variety of academic research projects and commercial projects. LLVM includes C and C++ front-ends (based on GCC 3.4), a front-end for a Forth-like language (Stacker), a young scheme front-end, and Java support is in development. LLVM can generate code for X86, SparcV9, PowerPC, or it can emit C code. This tutorial describes the LLVM virtual instruction set and the high-level design of the LLVM compiler system, We briefly describe how LLVM front-ends work and the high-level design of the LLVM target-independent code generator. We also briefly describe key development tools such as the pass framework and the automated compiler debugging support (bugpoint). | |
| 3:30-5:00pm | ORC: Open Research Compiler |
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Presenter: Chu-cheow Lim < chu-cheow.lim@intel.com > Xiaobin Feng < fxb@ict.ac.cn > Junchao Zhang < jczhang@ict.ac.cn > Download site: http://ipf-orc.sourceforge.net/ Abstract: The objective of the Open Research Compiler (ORC) project is to provide a leading open source ItaniumTM Processor Family (IA-64) compiler infrastructure to the compiler and architecture research community. This project is a collaboration between Intel Corp. and Chinese Academy of Sciences. We would like to provide a common infrastructure to encourage and facilitate compiler and architecture research. In the design of ORC, we stress on the following aspects: compatibility to other open source tools, robustness of the entire infrastructure, flexibility and modularity for quick prototyping of novel ideas, and leading performance among ItaniumTM Processor Family open source compilers. We would like to invite researchers to explore all aspects of compiler and architecture research on ORC, e.g. performance-driven optimizations, thread-level parallelism, co-design of software and hardware features, power management, design and implementation of type-safe languages, co-design of static and dynamic compilation, optimizations for memory hierarchies, etc. In this lecture, we will provide an overview of the ORC infrastructure and share our experience in using ORC in a speculative multi-threading research. | |
| 5:15-6:45pm | Trimaran: An Infrastructure for Research in Instruction-Level Parallelism |
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Presenter: Lakshmi Narasimhan Chakrapani < nsimhan@cc.gatech.edu > Download site: http://www.trimaran.org/download.html Abstract: Trimaran is an integrated compilation and performance monitoring infrastructure. The architecture space that Trimaran covers is characterized by HPL-PD, a parameterized processor architecture supporting novel features such as predication, control and data speculation and compiler controlled management of the memory hierarchy. Trimaran also consists of a full suite of analysis and optimization modules, as well as a graph-based intermediate language. Optimizations and analysis modules can be easily added, deleted or bypassed, thus facilitating compiler optimization research. Similarly, computer architecture research can be conducted by varying the HPL-PD machine via the machine description language HMDES. Trimaran also provides a detailed simulation environment and a flexible performance monitoring environment that automatically tracks the machine as it is varied. |
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