CMOS Integrated Circuits

Digital CMOS Integrated Circuits in 6H-SiC Using an Implanted P-Well Process

S. Ryu, K. T. Kornegay, J. A. Cooper, Jr. and M. R. Melloch

Supported by the Office of Naval Research.

CMOS technology is attractive for digital logic because it offers low power consumption, full rail-to-rail output swing, and greater noise margins than NMOS circuits. CMOS also provides active current sources for linear applications. Development of CMOS technology in SiC is expected to provide low power, high temperature circuits as well as reliable control circuitry for smart power ICs.

Cree Research was the first to report CMOS ICs in 6H-SiC [1,2]. Their process utilized an implanted n-well and deposited oxides, but due to other processing problems the PMOSFETs exhibited a very high threshold voltage. In this work, we use implanted p-wells and thermally grown oxides. The resulting PMOS threshold voltage is approximately -4.5 V, allowing circuit operation with a 5 V power supply [3, 4].

Figure 1 shows a cross section of a completed CMOS inverter in the implanted p-well process. The fabrication sequence is as follows: First, p-wells are formed on n-type epilayers doped at 8x10¹⁵cm^-3 by boron implantation. Al and N are then implanted through polysilicon masks to form P+ and N+ source/drain regions, respectively. NMOSFETs are formed on p-wells while the PMOSFETs are formed on n-type epilayers. Implants are annealed at 1600 C for 40 minutes in argon, followed by an 1150 C, 2 hour wet oxidation to form a 40 nm gate oxide layer. Polysilicon is then deposited and patterned to form the gates. Al-Ni is used for p-type ohmic contacts and Ni for n-type contacts. A silicon oxynitride layer is deposited as an intermetallic dielectric. Finally, vias are opened and interconnect metal is deposited and patterned.

Figure 1. Cross section of a CMOS inverter in the implanted p-well process. The p-well, P+ source regions, and N+ source regions are all formed by ion implantation. Both transistors have a polysilicon gate over a thermally grown oxide.

The CMOS test chip, shown in Fig. 2, contains a variety of digital circuits including inverters, NAND gates, NOR gates, XOR gates, half adders, flip-flops, and two 11-stage ring oscillators. All circuits operate properly from room temperature to 300 C on a single power supply at any voltage between 5 - 15 V. These are the first SiC CMOS circuits to operate on a 5 V supply. Figure 3 shows p-channel and n-channel MOSFET I-V characteristics at 300 C. Threshold voltages are 3.4 V and 1.4 V, respectively.

Figure 2. Photo of the CMOS test chip. Different regions are identified by letter, as follows: (A) differential amplifiers, (B) half adders, (C) inverters and flip-flops, (D) flip-flops, (E) NANDs, NORs, inverters, (F) XORs, (G) MOS capacitors, MOS gated diodes, TLM testers, MOSFETs, (H) ring oscillators.

Figure 3. Current-voltage characteristic of a 40 痠 by 5 痠 p-channel MOSFET (left) and a similar n-channel MOSFET (right), both at 300 C.

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[1] D. B. Slater, et al., Trans. 3rd Int'l High Temp. Elec. Conf., Vol. 2, pp. XVI-27 - XVI-32.

[2] D. B. Slater, et al., 54th Device Research Conf. Dig., pp. 162-163, June 1996.

[3] S. Ryu, K. T. Kornegay, J. A. Cooper, Jr., and M. R. Melloch, " 6H-SiC CMOS Digital ICs Operating on a 5V Power Supply," IEEE Device Research Conf., Ft. Collins, CO, June 23-25, 1997.

[4] S. Ryu, K. T. Kornegay, J. A. Cooper, Jr., and M. R. Melloch, " Digital CMOS ICs in 6H-SiC Operating on a 5V Power Supply," to appear in IEEE Trans. on Electron Devices, 1998.

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