NMOS Integrated Circuits

Silicon Carbide NMOS Integrated Circuits

Weize Xie, J. A. Cooper, Jr., and M. R. Melloch

Supported by the Ballistic Missile Defense Organization (administered by ONR)

In February 1994 we reported development of the first digital integrated circuits in SiC. The circuit technology is enhancement-load NMOS, with the load transistor operated in the non-saturating mode with a separate V_GG supply [1]. MOS transistors are formed in p-type epilayers of 6H-SiC by wet thermal oxidation at 1150 °C, followed by a 30 min. in-situ Ar anneal. Source and drain regions are formed by ion implantation of nitrogen and are activated by a high temperature Ar anneal. N-type ohmic contacts are formed by annealed nickel. The gate and interconnect metal is Al. These circuits included inverters, NAND and NOR gates, XNOR gates, RS flip flops, binary counters, and half adders. All circuits operated properly from room temperature to above 300 °C. The figures below show the binary counter and half adder circuits along with operating waveforms at room temperature and at 304 °C.

Figure 1. Left Side: SiC NMOS binary counter circuit and operating waveforms at room temperature. This circuit is a master-slave D-type flip-flop with the Q-bar output fed back to the D input to form a binary counter. Note that the output waveform switches at half the frequency of the input waveform. Right Side: SiC NMOS half adder circuit, truth table, and operating waveforms at 304 °C. As the A and B inputs change, note that the Sum and Carry outputs obey the binary rules in the truth table.

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[1] W. Xie, J. A. Cooper, Jr., and M. R. Melloch, "Monolithic NMOS Digital Integrated Circuits in 6H-SiC," IEEE Electron Device Lett., 15, 455 (1994).

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