SiC Power MOSFETs

Silicon Carbide Power MOSFETs

Jian Tan, Jayarama Shenoy, J. A. Cooper, Jr., M. R. Melloch, Pauline Matin, Sei-Hyung Ryu, Yu Li, and Jan Spitz

Supported by the Office of Naval Research

Power switching devices are reaching fundamental limits imposed by the low breakdown field of silicon, and substantial improvements can only be achieved by using a semiconductor with a higher breakdown field. In this project, we are developing power switching devices in silicon carbide (SiC), a compound semiconductor with a breakdown field about 10x higher than silicon.

SiC is unique among compound semiconductors in that its native oxide is SiO₂, the same oxide as silicon. This means that the workhorse power devices used in silicon, i.e. the power MOSFET, insulated gate bipolar transistor (IGBT), and various types of MOS-controlled thyristors (MCTs) can all be fabricated in SiC. Because of the higher breakdown field, SiC power devices can have specific on-resistances up to 400x lower than similar devices in silicon! This table lists the best reported SiC power device performance figures known to the webmaster.

The WBG group at Purdue is focusing on Schottky barrier diodes and power MOSFETs in SiC. Our MOSFET work is centered on two types of devices: DMOS and UMOS. The DMOS, or "Double-implanted MOS", power transistor is shown in Fig. 1. This device is analogous to the silicon "DMOS", or "double-Diffused MOS", power transistor except that the P base and N+ source regions are produced by ion implantation instead of thermal diffusion (diffusion is not practical in SiC because of the very low diffusion coefficients in the material). In this device, a positive bias on the polysilicon gate creates a surface inversion layer at the interface between the SiO₂ and the P-type SiC. Electrons flow from the N+ source along the inversion layer to the N- drift region. Upon reaching the drift region, electrons flow vertically to the N+ drain at the bottom. The thick, lightly doped N- drift region is needed to withstand a large drain voltage when the device is in the off state (gate at ground).

Figure 1. Cross section of a SiC ion-implanted "DMOS" power transistor.

In June 1996 we reported the first SiC DMOS power transistors [1,2]. These devices exhibited blocking voltages in excess of 760 V, approximately 3x higher than the best SiC MOSFETs up to that time. Specific on-resistance was 125 mOhm-cm² for the 760 V devices and 66 mOhm-cm² for 2 痠 channel length devices on the 500 V wafer. In June 1997 we introduced the first lateral DMOS (LDMOS) power transistors in SiC [3,4]. These devices exhibited a blocking voltage of 2.6 kV, which is still the highest blocking voltage for any SiC power switching device.

Most of the previous work in SiC power transistors has been devoted to the trench-gate or "UMOS" power transistor, shown schematically in Fig. 2. The electric fields in the blocking state (transistor OFF) are shown at the right. Looking at the blue (right-hand) plot, we note that the electric field in the oxide at the bottom of the trench is 2.5x higher than the peak field in the semiconductor. Such a high electric field will lead to catastrophic breakdown of the oxide. The field at the corner of the trench is even higher due to two-dimensional effects. This oxide breakdown problem represents a major limitation to the UMOSFET structure in SiC.

Figure 2. Cross section of a UMOS power transistor in silicon carbide. The electric field is illustrated on the right side for two regions within the device, the pn junction region and the MOS capacitor region. The field in the oxide at the base of the trench is 2.5x higher than the peak field in the semiconductor because of the discontinuity in dielectric constants at the interface.

We have recently introduced a novel UMOS structure with Integral Oxide Protection (IOP) [5] that limits the electric field in the trench oxide while simultaneously reducing on-resistance. This structure is shown in Fig. 3, along with the electric fields in the blocking state. The new P-type region in the bottom of the trench reduces the electric field at the oxide/semiconductor interface to zero, thereby protecting the oxide from high electric fields in the blocking state. The new N-type epilayer beneath the P-base prevents pinch-off of the conducting channel in the on-state and facilitates lateral current spreading into the drift region. The device in Fig. 3 also includes a lightly-doped N-type epilayer grown on the sidewalls of the trench. This layer converts the device into an accumulation-layer MOSFET, or "ACCUFET", increasing the MOSFET mobility and further reducing on-resistance.

Figure 3. Cross section of the recently-introduced IOP-UMOS power transistor. The electric field is illustrated on the right side for two regions within the device. The P-type region under the trench reduces the field in the oxide at the base of the trench to zero.

Figure 4 shows the static I-V characteristics of an IOP-UMOS ACCUFET in 4H-SiC [5]. The blocking voltage is 1400 V, which is 87% of the theoretical value for the 10 痠 drift region in our device. Breakdown is non-destructive, indicating that oxide failure does not occur. In fact, numerical simulations show that the peak electric field in the oxide is only 3 MV/cm at the blocking voltage of 1400 V. The specific on-resistance is 15.7 mOhm-cm², and the figure-of-merit V_B²/R_on is 125 MW/cm², the highest value ever reported for a power MOSFET in any material system and 25x higher than the theoretical limit for silicon power MOSFETs.

Figure 4. I-V characteristics of the IOP-UMOS ACCUFET in 4H-SiC at room temperature. The gate width is 3.168 mm, gate length is 1.2 痠, oxide thickness is 130 nm, and the active area is 1.728x10^-4 cm². The V_G=0 curve is swept to 1400 V four times, but the data points overlay one another.

The power device development described in this section is supported by a MURI grant from the Office of Naval Research (ONR). A PowerPoint-style presentation summarizing device development under this program (with emphasis on SiC power MOSFETs) can be viewed at our ONR/MURI Website.

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[1] J. N. Shenoy, M. R. Melloch, and J. A. Cooper, Jr., "High-Voltage Double-Implanted MOS Power Transistors in 6H-SiC," IEEE Device Research Conf., Santa Barbara, CA, June 24-26, 1996.

[2] J. N. Shenoy, J. A. Cooper, Jr., and M. R. Melloch,"High-Voltage Double-Implanted Power MOSFETs in 6H-SiC," IEEE Electron Device Lett., 18, 93 (1997).

[3] J. Spitz, M. R. Melloch, and J. A. Cooper, Jr., "2.6 kV 4H-SiC Power MOSFET," (late news) IEEE Device Research Conf., Ft. Collins, CO, June 23-25, 1997.

[4] J. Spitz, M. R. Melloch, J. A. Cooper, Jr., and M. A. Capano, "High-Voltage (2.6 kV) Lateral DMOSFETs in 4H-SiC," IEEE Electron Device Lett., 19, 100 (1998).

[5] J. Tan, J. A. Cooper, Jr., and M. R. Melloch,"High-Voltage Accumulation-Layer UMOSFETs in 4H-SiC", IEEE Electron Device Lett., 19, 487 (1998)

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