Silicon carbide (SiC) is currently under intensive investigation as an enabling material for a variety of new semiconductor devices in areas where silicon devices cannot effectively compete. These include high-power high-voltage switching applications, high temperature electronics, and high power microwave applications in the 1 - 10 GHz regime. SiC is attractive for these applications because of its extreme thermal stability, wide bandgap energy, and high breakdown field. The thermal stability promises long term reliable operation at high temperatures, but it also presents problems in certain fabrication steps, e.g. selective doping, where impurities must be introduced by ion implantation due to the exceedingly low diffusion coefficients of common dopant impurities at reasonable processing temperatures. Because of the wide bandgap energy (3.0 eV and 3.25 eV for the 6H and 4H polytypes respectively), leakage currents in SiC are many orders of magnitude lower than in silicon, and the intrinsic temperature is well over 800 C. These electronic properties make SiC attractive for high temperature electronics applications. In addition, the breakdown field in SiC is around 8x higher than in silicon. This is critical for power switching devices, since the specific on-resistance scales inversely as the cube of the breakdown field. Thus, SiC power devices are expected to have specific on-resistances 100 - 200x lower than comparable silicon devices [1]. Finally, SiC is the only compound semiconductor which can be thermally oxidized to form a high quality native oxide (SiO2). This makes it possible to fabricate MOSFETs, insulated gate bipolar transistors (IGBTs), and MOS-controlled thyristors (MCTs) in SiC.
Although it offers substantial advantages over silicon, SiC is still immature as a semiconductor material. Single crystal wafers of SiC have only been commercially available since around 1990 [2], and a number of critical material and processing issues are still under active investigation. The main limitations of the technology are in the area of crystal growth, and will be addressed in more detail below. In addition, certain critical fabrication processes are still under development. The most important of these fabrication issues are (i) activation of ion implanted impurities, (ii) formation of thermally stable low resistance ohmic contacts, and (iii) thermal oxidation (or deposition) of high quality dielectric films suitable for MOS devices. In the following sections we shall review the current status of the technology in these four critical areas: crystal growth, selective doping, ohmic contact formation, and thermal oxidation.
Before the mid-1950's, SiC was available only through the industrial Acheson process for making abrasive materials [3]. In 1955, a laboratory sublimation process for growing a-SiC crystals was developed by J. A. Lely at Philips Research Labs in Einhoven [4]. In the Lely process, the nucleation of individual crystals is uncontrolled and the resulting crystals are randomly-sized hexagonal-shaped a-SiC platelets [5]. In 1978, Tairov and Tsvetkov pioneered the growth of SiC single crystals by the physical vapor transport process. In 1983, Ziegler et al. [6] introduced a modified sublimation process for growing SiC single crystals, and in 1987, a research group under R. F. Davis at North Carolina State University (NCSU) announced the successful implementation of a seeded-growth sublimation process [7], a modification to the original Lely sublimation process. In the modified sublimation process, only one large crystal is grown, and this crystal consists of a single polytype. In this process, which is the basis of current commercial growth systems, a charge of polycrystalline SiC is heated in a graphite crucible containing argon at 200 Pa. A temperature gradient is established, with the polycrystalline SiC at about 2400 C and a seed crystal at about 2200 C. At these temperatures, SiC sublimes from the polycrystalline source and condenses on the cooler seed crystal.
In 1987, students from the NCSU group founded a small company, Cree Research, to produce SiC wafers commercially. The introduction of 25 mm single crystal wafers of 6H-SiC by Cree in 1990 catalyzed the current resurgence in SiC research and initiated an unprecedented level of device development in this material. At present, 35 mm diameter wafers of both 4H and 6H SiC are commercially available from Cree Research (Durham, NC, USA) and from Advanced Technology Materials, Inc. (Danbury, CT, USA). 50 mm diameter wafers are used in the production of blue LEDs at Cree, and 75 mm diameter wafers have been prototyped by both Cree and Westinghouse (now Northrup Grumman).
Current research in crystal growth centers around increasing the growth rate, increasing the wafer diameter, and reducing material defects. Current SiC wafers have etch pit densities on the order of 104 cm-2. These defects fall into three types, which have been classified as EP-1, EP-2, and EP-3 by Nakata, et al. [8]. The EP-1 defects are known as "micropipes", and are the open cores of giant screw dislocations with large Burgers vectors. Micropipes are holes, 0.5 - 10 microns in diameter, which run completely through the wafer and subsequently grown epilayers and are fatal to most kinds of devices. Micropipe densities have been steadily declining in recent years. Current Cree production wafers have micropipe densities in the 50-100 cm-2 range, and wafers with as few as 3.5 micropipes cm-2 have been reported [9].
Epitaxial layer growth is by chemical vapor deposition (CVD) on slightly off-axis substrates (3.5 degrees for 6H and 8 degrees for 4H). The use of off-axis substrates enables step-controlled epitaxy [10] in which steps on the growth surface expose several alternating silicon and carbon planes, thereby transferring stacking information which preserves the polytype in the epitaxially grown film. Typical growth rates are 1 - 5 microns/hour at a temperature of 1200 - 1500 C in SiH4, C3H8, and H2 [11]. In-situ doping is accomplished by the introduction of nitrogen (for n-type) and trimethylaluminum or triethylaluminum (for p-type). Recently, the development of site-competition epitaxy has extended the doping range achievable by CVD, with dopings as low as 1x1014 cm-3 and as high as >1x1019 cm-3 having been reported [12]. Very recently, E. Janzen, et al. [13] of Linkoping University reported a modified CVD technique capable of growing films up to 100 microns thick with a background doping level of 1x1014 cm-3. Carrier lifetimes in these lightly doped layers are on the order of 1 microsecond. These results are very exciting because they would theoretically enable the fabrication of power devices having blocking voltages in excess of 10 kV.
Selective doping of SiC is accomplished by ion implantation, since the diffusion coefficients of aluminum and nitrogen are so low that thermal diffusion is impractical. The implantation and activation of nitrogen to produce n-type regions is well understood, and activated concentrations above 1x1019 cm-3 can be obtained routinely. P-type selective doping, however, is an area of current research. The two common p-type dopants, aluminum and boron, produce relatively deep acceptor levels (211 meV and 300 meV respectively), but aluminum is generally used because of its smaller ionization energy. To minimize amorphization during implantation, it is common to implant at elevated temperatures, typically around 650 C for nitrogen and up to 1100 C for aluminum. Boron can be successfully implanted at room temperature. Kimoto, et al. [14, 15] report amorphization thresholds of 4x1015 cm-2 for nitrogen, 1x1015 cm-3 for aluminum, and 5x1015 cm-3 for boron.
Implant activation is accomplished by a high temperature anneal in argon. Ghezzo, et al. [16] report a series of isochronal (30 min.) anneals of nitrogen in 6H-SiC for various implant temperatures. They obtain a sheet resistance of 906 Ohms/square with a 1300 C anneal following implantation at 600 - 700 C. Pan, et al. [17] investigated the effect of anneal time on nitrogen implants in 6H-SiC at three temperatures: 1200, 1050, and 900 C. They found an optimum anneal time at each temperature, with the optimum times being < 5 min., 40 min., and 40 hr. at 1200, 1050, and 900 C, respectively. Minimum sheet resistances obtained at the three temperatures were 700, 810, and 1005 Ohms/square, respectively.
Kimoto, et al. [15] report sheet resistivities as low as 22 kOhms/square for aluminum implanted into 6H-SiC at room temperature. They investigated implant doses ranging from 1x1014 to 1x1016 and anneal temperatures from 1200 - 1500 C, with all anneals conducted for 30 min. in argon. The minimum sheet resistivity occurred at a dose of 2x1015 cm-3 and an anneal temperature of 1500 C. Redistribution of aluminum is negligible at 1500 C. In the anneal, they utilized an RF induction heated furnace, which allows very fast heating (40 C/sec) and may help to minimize defect formation during annealing. Rao, et al. [18] investigated the implantation of aluminum, along with the co-implantation of Al/C and Al/Si, into 6H-SiC at an in-situ temperature of 850 C. The implants were annealed at temperatures of 1500, 1600, and 1650 C for 45 min. in a ceramic furnace with a heating rate of 10 C/min. and a cooling rate of 3 C/min. The minimum sheet resistivities were 4.6 and 1.5 kOhms/square for aluminum implanted at a dose of 2.66x1015 cm-2 and annealed at 1500 and 1600 C, respectively. The co-implantations did not result in improvement in aluminum activation. In order to preserve surface morphology at these anneal temperatures, the samples were encapsulated in a SiC crucible during annealing. Even with this encapsulation, surface morphology deteriorated at 1650 C.
Ohmic contacts are of great importance to power devices, since the high current densities give rise to intolerable voltage drops across even small resistances. Ohmic contacts to n-type material are typically formed by annealed nickel. The contacts are annealed at high temperatures, typically between 850 - 1050 C, in argon or vacuum. Specific contact resistivities < 5x10-6 Ohm-cm2 can be obtained to heavily doped n-type layers [19]. Contacts to p-type material have been more difficult. The p-type contacts are typically formed by annealed aluminum, or by a bilayer of aluminum covered with titanium. Anneal temperatures are similar to those used for nickel contacts, but the contact resistivities are in the 10-3 to 10-5 Ohm-cm2 range, depending on doping density [20]. Very recently, Ostling and Lundberg [21] reported contact resistivities to p-type 6H-SiC in the mid-10-6 Ohm-cm2 range using sequential electron beam evaporation of cobalt and silicon, followed by a two step vacuum annealing process at 500 C and 900 C.
The thermal integrity of the metallization system is of importance for high temperature applications. Nickel ohmic contacts used for n-type material have been shown to be stable to very high temperatures (negligible change in resistance after 329 hours at 650 C or after short thermal cycles to 1300 C) [20], but aluminum p-type contacts will not be capable of high temperature operation. The use of metal silicides, as recently reported for p-type ohmic contacts [21], will enable operation to much higher temperatures.
SiC is the only compound semiconductor which can be thermally oxidized to form a device-quality native oxide, SiO2. This capability removes one of the basic limitations of all other compound semiconductors and places SiC in a unique position to compete with silicon. To take full advantage of this unprecedented opportunity, every effort must be made to advance thermal oxidation technology so that SiC MOS interfaces have electrical characteristics comparable to those obtained on silicon.
SiC is oxidized using the same equipment and techniques used for silicon, but the oxidation rates are slower. In the oxidation process, the oxidizing species diffuses through the growing film and reacts with SiC at the oxide/semiconductor interface. The reaction products are SiO2 and CO, with the CO molecules diffusing out through the growing oxide. The reaction kinetics are similar to silicon, with the early portion of the oxidation process being reaction rate limited and the later stages diffusion limited. However, oxidation rates depend strongly on the crystalline surface being oxidized, with the (0001- ) carbon face oxidizing 5-10x faster than the (0001) silicon face. The oxidation rate of (11- 00) and (112- 0) "a-axis" surfaces is intermediate between that on the silicon and carbon faces. Oxidation rate is also a weak function of substrate doping density, increasing for more heavily doped material.
Early papers on the electrical properties of the MOS interface on SiC reported nearly ideal interfaces, comparable to those obtained on silicon. These early reports proved inaccurate, however, because the authors failed to take into account the effect of the wide bandgap on conventional MOS analysis techniques. At room temperature, interface states more than about 0.5 eV away from the band edges cannot respond fast enough to follow changes in DC bias during capacitance-voltage (CV) sweeps [22]. As a result, these deep states do not change their charge state, and exert no influence on the CV characteristic, thereby going undetected. Careful measurements conducted at elevated temperatures (250 - 350 C) revealed interface state densities in the low 1011 eV-1 cm-2 range on n-type SiC [23, 24] and in the mid-to-upper 1011 eV-1 cm-2 range on p-type SiC [22, 23]. MOS capacitors formed on n-type material exhibit a flat band voltage near zero, while similar capacitors on p-type material have large negative flat band voltages (typically -7 to -15 V, depending upon oxide thickness). These observations lead many investigators to conclude that the MOS interface on p-type SiC is inferior to that on n-type SiC. Speculation centered on the role of the aluminum dopant in p-type material, since SIMS studies indicated that aluminum is incorporated in the growing SiO2 film at about half the concentration present in the semiconductor.
In the last few years, however, the picture has improved considerably. Work at our laboratory and other locations, including Laboratoire de Physique des Composants a Semiconducteurs (LPCS) and Cree Research, has lead to a reduction in interface state density on p-type SiC to the low 1011 eV-1 cm-2 range [22], comparable to that obtained on n-type SiC. Several studies [22, 25, 26] have shown that the aluminum dopant is not responsible for either interface states or fixed charges on p-type material. The flat band voltage of p-type SiC MOS capacitors remains negative, while on n-type SiC it is near zero. However, much of this difference in flat band voltage is due to the difference in position of the Fermi energy on n-type and p-type MOS capacitors (near the conduction band on n-type and near the valence band on p-type), and does not necessarily indicate a larger fixed oxide charge on p-type SiC [27].
Most of the MOS studies to date have been confined to the (0001) silicon face of 6H-SiC. Recently, we have shown that MOS interfaces on 4H SiC have interface state and fixed oxide charge densities comparable to those on 6H [28]. However, MOS interfaces formed on the (11- 00) and (112- 0) "a-axis" surfaces of 6H-SiC are definitely inferior to those on the silicon face [24], with interface state densities approximately 6 - 10x higher. The "a-axis" surfaces lie perpendicular to the basal plane of the hexagonal lattice, and therefore contain an equal number of silicon and carbon atoms per unit area. Evidence is mounting that the presence of carbon on the plane being oxidized leads to serious degradation in the resulting interface quality, but a clear picture of the microscopic details has yet to emerge. This is a critical issue, because these surfaces are important for several types of power switching devices, including trench MOSFETs, trench IGBTs, and trench MCTs.
One final area which is attracting attention is that of deposited insulators. One reason is the desire for an insulator having a dielectric constant comparable to or higher than that of the substrate. This is important for power devices because the electric field in SiO2 is approximately 2.5x higher than the peak field in SiC, due to the dielectric constant ratio. Thus, in many cases the maximum blocking voltage of SiC power devices is limited by the SiO2 and not by the semiconductor. An insulator having a higher dielectric constant would have a correspondingly lower electric field at a given operating voltage. AlN and TiO2 are among the insulators under investigation, but this work is still at a very preliminary stage.
At this time, SiC appears poised to compete in several important commercial markets, including high-voltage high-power switching devices and high temperature electronics. However, in order to become economically viable, several critical materials and processing issues still need to be solved. The most serious issue is the immature state of the crystal growth technology, where increases in wafer size and quality are urgently needed. Device fabrication research is focusing on activation of implanted dopants, development of thermally stable low resistance ohmic contacts to p-type material, and formation of high quality MOS interfaces, particularly on a-axis surfaces.
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